Stratix IV GX EP4SGX230
28,000 logic elements (L)
17,133K total memory Kbits
1,28 18x18-bit multipliers blocks
2 PCI Exprs hard IP blocks
74 user I/Os
8 phase locked loops (PLLs)
Stratix IV GX EP4SGX530
531,200 logic elements (L)
27,376K total memory Kbits
1,024 18x18-bit multipliers blocks
4 PCI Exprs hard IP Blocks
74 user I/Os
8 phase locked loops (PLLs)
FPGA 配置
JTAG and Fast Pive Parallel (FPP) configuration
內(nèi)建 U Blaster 電路
內(nèi)存
64 Flash with a 16-bit data bus
2 ZBT SSRAM
I2C EEPROM
Two DDR2 SO-DIMM Sockets
400 MHz clock rate
Maximum theoretical bandwidth of over 102 Gbps
Up to 8-Gbyte capacity in total
SD Card Socket
支持 SPI 以及 SD 1-bit 兩種 SD Card 讀取模式
按鈕，開關(guān)與 LED
4 個(gè)按鈕
4 個(gè)滑動(dòng)開關(guān)
8 個(gè) LED
8 位 DIP 開關(guān)
2 個(gè)七段數(shù)碼顯示管
2 個(gè)的七段數(shù)碼顯示管
On-Board Clocks
3 Programmable PLLs configured via FPGA
o HSMA, HS transceiver clock source
o SATA reference clock
o FPGA LVDS clock input
50MHz/100MHz oscillator
SMA 接頭
2 SMA connector for external transceiver clock input
4 SMA connector for LVDS clock input/output
2 SMA connectors for clock output
1 SMA connector for external clock input
4 個(gè) SATA 接口
Support SATA 3.0 standard 6Gbps signaling rate
Two host and two device ports
4 個(gè)千兆以太網(wǎng)接口
Integrated 1.25 GHz SERD
PCI Exprs x8 Edge Connector
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Connection tablished with PC motherboard with x8 or x16 PCI Exprs slot
Two 172-pins High Speed Mezzanine Card (HSMC)
2 female-HSMC connectors
I/O voltage 2.5V
Total of 12 high-speed transceivers at 8.5 Gbps
Total of 38 LVDS pair at 1.6 Gbps
兩組40個(gè)接腳擴(kuò)充槽
72個(gè) I / O引腳及4個(gè)電源和接地線，拉到40-pin 擴(kuò)充槽
用于40-pin 擴(kuò)充槽的排線可利用 IDE 硬碟的40-pin 排線
I/O voltage 3.0V
U主/從控制器
合通用串行總線規(guī)范2.0修訂版標(biāo)準(zhǔn)
支持?jǐn)?shù)據(jù)傳輸、全速傳輸與低速傳輸
Support both U host and device
3種U 接口 (one te mini-AB for host/device and two te A for host)
支持PIO與DMA模
電源
28,000 logic elements (L)
17,133K total memory Kbits
1,28 18x18-bit multipliers blocks
2 PCI Exprs hard IP blocks
74 user I/Os
8 phase locked loops (PLLs)
Stratix IV GX EP4SGX530
531,200 logic elements (L)
27,376K total memory Kbits
1,024 18x18-bit multipliers blocks
4 PCI Exprs hard IP Blocks
74 user I/Os
8 phase locked loops (PLLs)
FPGA 配置
JTAG and Fast Pive Parallel (FPP) configuration
內(nèi)建 U Blaster 電路
內(nèi)存
64 Flash with a 16-bit data bus
2 ZBT SSRAM
I2C EEPROM
Two DDR2 SO-DIMM Sockets
400 MHz clock rate
Maximum theoretical bandwidth of over 102 Gbps
Up to 8-Gbyte capacity in total
SD Card Socket
支持 SPI 以及 SD 1-bit 兩種 SD Card 讀取模式
按鈕，開關(guān)與 LED
4 個(gè)按鈕
4 個(gè)滑動(dòng)開關(guān)
8 個(gè) LED
8 位 DIP 開關(guān)
2 個(gè)七段數(shù)碼顯示管
2 個(gè)的七段數(shù)碼顯示管
On-Board Clocks
3 Programmable PLLs configured via FPGA
o HSMA, HS transceiver clock source
o SATA reference clock
o FPGA LVDS clock input
50MHz/100MHz oscillator
SMA 接頭
2 SMA connector for external transceiver clock input
4 SMA connector for LVDS clock input/output
2 SMA connectors for clock output
1 SMA connector for external clock input
4 個(gè) SATA 接口
Support SATA 3.0 standard 6Gbps signaling rate
Two host and two device ports
4 個(gè)千兆以太網(wǎng)接口
Integrated 1.25 GHz SERD
PCI Exprs x8 Edge Connector
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Connection tablished with PC motherboard with x8 or x16 PCI Exprs slot
Two 172-pins High Speed Mezzanine Card (HSMC)
2 female-HSMC connectors
I/O voltage 2.5V
Total of 12 high-speed transceivers at 8.5 Gbps
Total of 38 LVDS pair at 1.6 Gbps
兩組40個(gè)接腳擴(kuò)充槽
72個(gè) I / O引腳及4個(gè)電源和接地線，拉到40-pin 擴(kuò)充槽
用于40-pin 擴(kuò)充槽的排線可利用 IDE 硬碟的40-pin 排線
I/O voltage 3.0V
U主/從控制器
合通用串行總線規(guī)范2.0修訂版標(biāo)準(zhǔn)
支持?jǐn)?shù)據(jù)傳輸、全速傳輸與低速傳輸
Support both U host and device
3種U 接口 (one te mini-AB for host/device and two te A for host)
支持PIO與DMA模
電源
